The present disclosure relates to integrate circuit (IC) interconnects, and more specifically, to methods of forming an interconnect with a via-wire conductive structure using a wire trench etching first process and a double layered sidewall spacer. A related interconnect, and a related method using the wire trench etching first process, are also disclosed.
Integrated circuits include a number of interconnect layers that allow for electrical interconnection of devices in various layers such as transistors, resistors, capacitors, etc. Each interconnect layer typically includes wiring that laterally interconnects structures, or vias that vertically interconnect structures. Each interconnect layer typically includes a dielectric layer into which the wires and/or vias, which are collectively and individually referred to herein as interconnects, are formed. Each interconnect layer is typically separated by an etch stop layer that is used to control etching during formation of the interconnect layers.
Damascene is a process in which an interconnect pattern is first lithographically defined in a layer of dielectric, then metal is deposited to fill resulting wire trench openings or via openings, and then excess metal is removed by means of chemical-mechanical polishing (planarization). Dual damascene is a similar process in which interconnect patterns define wire trench openings and via openings together prior to metal deposition.
FIGS. 1-3 show cross-sectional views of a conventional dual damascene process for forming a via-wire conductive structure in a dielectric layer 10 of an interconnect layer 12. Interconnect layer 12 is positioned over a lower interconnect layer 14 including, as shown in FIG. 1, a number of vias 16 and a wire 17 (16 and 17 are underlayer metal lines). Interconnect layers 12, 14 are separated by etch stop layer 18, e.g., nitrogen-doped carbide (NDC) or nitrogen-doped silicon carbide (SiCxNyHz)(NBLOK). In this example, a dual damascene process for creating via-wire structure in interconnect layer 10 includes forming a hard mask 20 over dielectric layer 10 including a wire trench pattern therein, then forming a via mask 22 having a via opening pattern therein over hard mask 20. As shown in FIG. 2, an etching is then carried out to etch via openings 26 for vias into dielectric layer 10. At this stage, via openings 26 expose etch stop layer 18. As shown in FIG. 3, the via etching is followed by a wire trench etching to etch wire trench opening 28 for a wire (wire will couple vias formed in via openings 26). Each etching may include, for example, a reactive ion etch (RIE).
FIG. 4 shows an enlarged cross-sectional view of a portion of FIG. 3 after metal has been deposited in openings 26, 28. More particularly, after etch stop layer 18 is removed, conventional processing continues with a barrier liner 30 (e.g., refractory metal) deposition into via opening 26 and wire opening 28, then a metal 32 (e.g., copper) deposition and a planarization to create a via-wire conductive structure 40 including a via 42 and a wire 44. Via 44 preferably lands on via 16 or another conductive structure, e.g., a wire or device, in lower interconnect layer 14.
A challenge with this process is that the trench etching (FIG. 2) to create wire trench opening 28 for wire 44 can impact aspects of via opening 26 for via 42, and hence the operation of via 42. First, as shown in FIG. 4, an enlarged chamfer 46 can be created during trench etching (FIG. 3) that can cause a short of via 42 to, for example, wire 17 therebelow (or another via in the same location as wire 17). The ability for enlarged chamfer 46 to create a short can be increased, for example: by an overlay error (OVL) in the mask patterning for via 42, via 16, wire 44 and/or wire 17; a non-uniformity or an angle variation of via 42 and/or via 16; and/or a high voltage strip fail; among other things. Second, as shown in a plan view in FIG. 5, the trench etching coming after via etching can create a via bumpout 50 that when filled with metal can short via 42 (shown in phantom under wire 44) to, for example, another wire 44A above via 42. In particular, the trench etching can erode metal liner 30 (FIG. 4) that can allow for the short. Even if a short does not immediately result, the occurrence of shorts can still be increased because of the increased chances of time dependent dielectric breakdown (TDDB) caused by the overlay error or liner erosion. These challenges may be more profound near a wafer edge due to increased etch stop layer erosion during dielectric reactive ion etching (RIE) at the edge, but they can be observed in any interconnect layer.